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Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard

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7 Author(s)
Dam, A.C. ; Dept. of Electr. Eng. & Mater. Comput. Sci., Twente Univ., Enschede ; Lammertink, M.G.J. ; Rovers, K.C. ; Slagman, J.
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This paper addresses the implementation of Reed-Solomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the digital media broadcasting (DMB). The most critical element of the Reed-Solomon algorithm is implemented on two different reconfigurable hardware architectures: an FPGA and a coarse-grained architecture: the Montium, The remaining parts are executed on an ARM processor. The results of this research show that a co-design of the ARM together with an FPGA or a Montium leads to a substantial decrease in energy consumption. The energy consumption of syndrome calculation of the Reed-Solomon decoding algorithm is estimated for an FPGA and a Montium by means of simulations. The Montium proves to be more efficient

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Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on

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