By Topic

Dependable Design for FPGA Based on Duplex System and Reconfiguration

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kubalik, P. ; Dept. of Comput. Sci. & Eng., Czech Tech. Univ., Prague ; Dobias, R. ; Kubatova, H.

A technique for highly reliable digital design in FPGAs is presented. Two FPGAs are used for duplex system design, but better dependability parameters are obtained by combination of totally self checking blocks based on parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained by XILINX FPGA implementation by EDA tools. The dependability model and dependability calculations are presented

Published in:

Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on

Date of Conference:

0-0 0