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A 6-bit, 1.2 GHz Interleaved SAR ADC in 90nm CMOS

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4 Author(s)
Dondi, S. ; Dipt. di Ingegneria dell'' Informazione, Parma Univ. ; Vecchi, D. ; Boni, A. ; Bigi, M.

A 6-bit time-interleaved analog-to-digital converter for ultra-wide band applications is proposed. The structure consists of seven successive approximation A/D converters designed to pursue high speed and low power consumption. A merged-capacitor technique is implemented in the DAC, while the successive approximations register is based on a single-row architecture with D-FF's. The converter, designed in ST 90nm CMOS technology exhibits a maximum sampling frequency of 1.2 GHz at 1 V supply with a 500 mV input range and 16 mW of power consumption. The simulated figure of merit is 0.3 pJ/conv

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Research in Microelectronics and Electronics 2006, Ph. D.

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