DAC nonlinearity and residue gain error correction in a pipelined ADC using a split-ADC architecture

A split-ADC architecture is used to calibrate both the non-linearity errors introduced by capacitor mismatches in the DAC, and gain errors in the residue amplifier of the first stage in a pipelined ADC. The background scheme only requires 10
⁵
clock cycles to perform the calibration to more than 12b accuracy. Simulated in Simulink and Spice, the digital calibration scheme improves the ADC's SNDR/SFDR from 54dB/58dB before calibration to 78dB/85dB after calibration