By Topic

DAC nonlinearity and residue gain error correction in a pipelined ADC using a split-ADC architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ahmed, I. ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont. ; Johns, D.A.

A split-ADC architecture is used to calibrate both the non-linearity errors introduced by capacitor mismatches in the DAC, and gain errors in the residue amplifier of the first stage in a pipelined ADC. The background scheme only requires 105 clock cycles to perform the calibration to more than 12b accuracy. Simulated in Simulink and Spice, the digital calibration scheme improves the ADC's SNDR/SFDR from 54dB/58dB before calibration to 78dB/85dB after calibration

Published in:

Research in Microelectronics and Electronics 2006, Ph. D.

Date of Conference:

0-0 0