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DAC nonlinearity and residue gain error correction in a pipelined ADC using a split-ADC architecture

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2 Author(s)
Ahmed, I. ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont. ; Johns, D.A.

A split-ADC architecture is used to calibrate both the non-linearity errors introduced by capacitor mismatches in the DAC, and gain errors in the residue amplifier of the first stage in a pipelined ADC. The background scheme only requires 105 clock cycles to perform the calibration to more than 12b accuracy. Simulated in Simulink and Spice, the digital calibration scheme improves the ADC's SNDR/SFDR from 54dB/58dB before calibration to 78dB/85dB after calibration

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Research in Microelectronics and Electronics 2006, Ph. D.

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