A Novel Parallel Architecture of a Reconfigurable Video Processor based on Multi-radix number systems

The potential need of the video compression algorithms is to decode a digital video bit-stream in different ways and it is likely that a number of different video representations may need to coexist in a single system thereby requiring a high degree of flexibility with a high performance. This paper presents a high-performance re-configurable video architecture which eliminates the inflexibility of ASICs and inadequacy of FPGAs to offer highest possible performance at lowest silicon cost. The proposed architecture is based on exploitation of spatial and temporal both types of parallelism inherent in many video applications. SIMD machines are often used for spatial parallelism To overcome the limitation of the SIMD machines, here Processing Elements (PEs) are replaced by configurable functional blocks (CFBs) consisting of high speed adders, multipliers, trigonometric and square root computing units, etc. The CFBs under the control of a Master Control Unit (MCU) will be configured to execute the task of a particular function in parallel