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Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications

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1 Author(s)
Lewis, S.H. ; Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

The author examines the effect of the stage resolution on some important characteristics of monolithic, pipelined, multistage, analog-to-digital converters (ADCs) with identical stages for video-rate applications. These characteristics are the linearity, speed, area, and power dissipation. It is found that although large stage resolution is desirable from a linearity standpoint, the effect of stage resolution on linearity is small if the ADC uses redundancy and digital correction and if the magnitude of the interstage gain is at least two. Also, minimizing the stage resolution maximizes the conversion rate and minimizes both the die area and the power dissipation

Published in:

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:39 ,  Issue: 8 )

Date of Publication:

Aug 1992

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