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Design Space Exploration for Rapid Development of DSP Applications

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5 Author(s)
Le Moullec, Y. ; Center for Embedded Syst., Aalborg Univ. ; Christensen, S.S. ; Chenpeng, W. ; Koch, P.
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In this paper a new methodology for accelerating the development cycle of DSP applications is presented. This methodology is composed of three steps 1) algorithm design with Matlab (mathworks), 2) algorithmic-level characterization and parallelism exploration using Design-Trotter SoC framework (LESTER/CISS) and 3) FPGA hardware synthesis with DK Design Suite (Celoxica). We have applied the proposed methodology to explore the design space of a RAKE receiver. The results show that by using this methodology, designers can rapidly converge from specification phases to the final synthesis of the system. The parallelism information provided by Design-Trotter has been shown extremely useful to develop the Handel-C description of the application, enabling a rapid synthesis of the system with DK Design Suite. The time-to-market factor is thus significantly reduced

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Information, Communications and Signal Processing, 2005 Fifth International Conference on

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