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Mining global constraints for improving bounded sequential equivalence checking

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2 Author(s)
Weixin Wu ; Dept. of Electr. & Comput. Eng., Virginia Tech., Blacksburg, VA ; Hsiao, M.S.

In this paper, we propose a novel technique on mining relationships in a sequential circuit to discover global constraints. In contrast to the traditional learning methods, our mining algorithm can find important relationships among several nodes efficiently. The nodes involved may often span several time-frames, thus improving the deducibility of the problem instance. Experimental results demonstrate that the application of these global constraints to SAT-based bounded sequential equivalence checking can achieve one to two orders of magnitude speedup. In addition, because it is orthogonal to the underlying SAT solver, it can help to enhance the efficacy of typical SAT based verification flows

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Design Automation Conference, 2006 43rd ACM/IEEE

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