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A network security processor design based on an integrated SOC design and test platform

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7 Author(s)
Chen-Hsing Wang ; Dept. of Elec. Eng., NTHU, Hsinchu ; Chih-Yen Lo ; Min-Shenq Lee ; Jen-Chieh Yeh
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In this paper we present a generic network security processor (NSP) design suitable for a wide range of security related protocols in wired or wireless network applications. Following the platform-based design methodology, we develop four specific platforms, i.e., architecture platform, EDA platform, design-for-testability (DFT) platform, and prototyping platform, for our NSP design. With these platforms, design of the NSP chip becomes more efficient and systematic. A prototype chip of the NSP has been implemented and fabricated with a 0.18 mum CMOS technology. The chip area is 5 mm times 5 mm (with 1M gates approximately), including I/O pads. The operating clock rate is 80 MHz. The best performance of the crypto-engines is 1.025 Gbps for AES, 1.652 Mbps for RSA, 125.9/157.65 Mbps for HMAC-SHA1/MD5, and 2.56 Gbps for random number generator. Comparison result shows that our NSP is efficient in terms of performance, flexibility and scalability

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Design Automation Conference, 2006 43rd ACM/IEEE

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