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SystemC transaction level models and RTL verification

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1 Author(s)
Swan, S. ; Cadence Design Syst., Inc., San Jose, CA

This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are being reused for RTL verification. The paper discusses how the task of system verification is changing as systems become more complex and it discusses how companies are striving to eliminate fragmentation within their design and verification flows by leveraging SystemC transaction level models

Published in:

Design Automation Conference, 2006 43rd ACM/IEEE

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