By Topic

Investigation Of A New Genetic Algorithm Designed For System-On-Chip Realization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Zhenhuan Zhu ; Loughborough Univ., Loughborough ; Mulvaney, D. ; Chouliaras, V.

This paper introduces a novel genetic algorithm whose properties have been purposely designed to be suited to hardware implementation. This is distinct from previous hardware designs that have been realized directly from conventional genetic algorithm approaches. To be suitable for hardware implementation, we propose that a genetic algorithm should attempt to both minimize final layout dimensions and reduce execution time while not compromising algorithmic performance. Consequently, the new genetic algorithm specifically aims to keep the requisite silicon area to a minimum by incorporating a monogenetic strategy that retains only the optimum individual, resulting in a dramatic reduction in the memory requirement and obviating the need for crossover circuitry. The results given in this paper demonstrate that new approach improves on a number of existing hardware genetic algorithm implementations in terms of the quality of the solution produced, the calculation time and the hardware component requirements.

Published in:

Evolutionary Computation, 2006. CEC 2006. IEEE Congress on

Date of Conference:

0-0 0