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A possible scaling limit for enhancement-mode GaAs MESFETs in DCFL circuits

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2 Author(s)
Hirose, M. ; Toshiba Corp., Kawasaki, Japan ; Uchitomi, Naotaka

A possible scaling limit for ion-implanted GaAs MESFETs with buried p-layer LDD structure has been numerically investigated. A Schottky-contact model with a thin interfacial layer and interface states was used to simulate the Schottky-barrier height of a scaled-down MESFETs. When enhancement-mode MESFETs in direct-coupled FET logic (DCFL) circuits are scaled down, the gate length can be reduced to 0.21 μm at an interface-state density of 6.6×1012 cm-2·eV-1, when the barrier height is greater than 0.6 V, the threshold voltage is less than 0.1 V, and the channel aspect ratio is 8

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Electron Devices, IEEE Transactions on  (Volume:39 ,  Issue: 12 )