New Design of RNS Subtractor for modulo 2n+ 1

This paper presents a high-speed subtractor in residue number system (RNS). In this paper, utilizing the conversion of single range unsigned (SRU) number system to single range signed (SRS) number system, we have made the subtraction more rapidly. Moduli set of (2
ⁿ
- 1, 2
ⁿ
, 2
ⁿ
+ 1) is very attractive and has so many advantages over the other moduli sets, when realizing the related circuits. Beside the arithmetic operation delays are restricted by modulo 2
ⁿ
+ 1. Therefore, this method especially for above moduli will be very useful. By this fact, n + 1 bit wide subtractors are reduced to n bit wide subtractor. It is shown that the proposed design delay is about n/(n + 1) percent of existing one. This property has lead to more efficient realization of VLSI aspects