A Low-Cost Low-Power CMOS Time-to-Digital Converter Based on Pulse Stretching

A low-cost and low-power CMOS time-to-digital converter (TDC) with 50-ps time resolution is proposed in this paper. The reference clock frequency of the TDC is 80 MHz and the input range is theoretically unlimited. Two parallel time interpolators are used to improve the resolution by pulse stretching. In addition to conventional current ratio and capacitor ratio, the duty cycle of the discharging clock is also incorporated to adjust the stretch factor to reduce the power consumption and chip area dramatically. The interpolators are based on analog dual-slope conversion. The time resolution is measured as 50 ps and the integral nonlinearity (INL) error is within
$pm 1.1$
LSB for input range up to 250ns. The temperature drift of the measured resolution is
$-15.2hbox%$
to
$+13hbox%$
over a temperature range of
$-$
40
$^circ$
C to 80
$^circ$
C, which is significantly smaller than
$pm125hbox%$
drift over 100
$^circ$
C temperature range in pervious work. The voltage drift is 3.8 ps/V or equivalently
$pm 3.5%$
over 3.0–4.0 V supply voltage range. The measured resolution is within 49.8 ps to 52.7 ps for six packaged chips and the chip size is merely 0.5 mm
$, times ,$
0.45mm as fabricated in the TSMC 0.35-
$mu$
m CMOS digital process. The power consumption is 0.75mW, enormously reduced from hundreds of milliwatts of the predecessors, at 100 k samples/s and the measurement rate can achieve as high as 150 k samples/s.