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An On-Sensor Bit-Serial Column-Parallel Processing Architecture for High-Speed Discrete Fourier Transform

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3 Author(s)
Eki, T. ; Adv. Autom. Co., Fujisawashi ; Kawahito, Shoji ; Tadokoro, Y.

This brief presents a discrete Fourier transform (DFT) processor based on a bit-serial column-parallel processing architecture suitable for integrating it on CMOS image sensors. Using a column-parallel A/D converter (ADC) array, column-line sensor outputs of the two-dimensional image array are digitized. The ADC outputs are sliced to one bit and are given to the bit-serial column-parallel DFT processor from the MSB to the LSB. A high-speed and cost-effective implementation can be expected. In the case of 256times256-point DFT for 8-b image data, the processing time is estimated to be 2 ms at a clock frequency of 100 MHz, which corresponds to the 500-frames/s real-time processing

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:53 ,  Issue: 8 )

Date of Publication:

Aug. 2006

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