Referenced Items are not available for this document.
We present a flash ADC design technique that compensates for static nonlinearity of the up-front track-and-hold circuit, so that high speed and high linearity can be obtained at the same time. The proposed technique functions in synergy with a new background comparator offset correction scheme. The excess quantization noise generated due to the background autozero process is derived. We demonstrate the efficacy of our techniques with measurement results for a 160 MSPS 6-bit flash converter designed in a 0.35-mum CMOS process. The ADC consumes 50 mW from a 3.3 V power supply and has an 5.3 effective number of bits (ENOB) at Nyquist
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:41
,
Issue:
9
)
Date of Publication: Sept. 2006
- Page(s):
- 1959 - 1969
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 9080649
- Digital Object Identifier :
- 10.1109/JSSC.2006.880601
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 28 August 2006
- Issue Date :
- Sept. 2006
- Sponsored by :
- IEEE Solid-State Circuits Society
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