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Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

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4 Author(s)
K. -H. Park ; Sch. of Electron. & Electr. Eng., Kyungpook Nat. Univ., Daegu ; K. -R. Han ; Y. M. Kim ; J. -H. Lee

A novel modified saddle MOSFET to be applied to sub-50-nm DRAM technology with high performance and easy scalability is proposed, and its characteristics at a given recess open width of 40 nm is studied by device simulation. The proposed device has ~ 21% lower gate capacitance and lower Ioff by two orders of magnitude than a conventional saddle device under nearly the same Ion. In addition, the proposed device showed less threshold voltage sensitivity to the corner shape and lower gate delay time (CV/I) by ~ 30% than the conventional recess channel device while keeping nearly the same Ioff

Published in:

IEEE Electron Device Letters  (Volume:27 ,  Issue: 9 )