By Topic

An Low Complexity Hardware Implementation of MIMO Detector with Application to WLAN

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Chanho Yoon ; Next Generation Wireless LAN Res. Team, Electron. & Telecommun. Res. Inst., Daejeon ; Eunyoung Choi ; Jungbo Son ; Sok-Kyu Lee
more authors

In this paper, we describe a FPGA implementation of MIMO detector for future wireless communication system with application to wireless LAN, targeted for upcoming 802.11n standard. The MIMO detector assumes 2 transmit and 3 receive antennas. In soft-output demapper, we apply channel state information which effectively weights reliability information to soft-decision output bits for enhanced link-level performance. The implementation complexity is significantly reduced by avoiding repeated pseudo-inverse calculation for interference cancellation of every received symbol vector. Furthermore, the overall processing time and fabrication area it takes can be significantly reduced by applying bit reduction technique

Published in:

Vehicular Technology Conference, 2006. VTC 2006-Spring. IEEE 63rd  (Volume:5 )

Date of Conference:

7-10 May 2006