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An Low Complexity Hardware Implementation of MIMO Detector with Application to WLAN

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5 Author(s)
Chanho Yoon ; Next Generation Wireless LAN, Research Team, ETRI, 161 Gajeong-dong Yuseong-gu, Daejeon, 305-700, KOREA. Email: ; Eunyoung Choi ; Jungbo Son ; Sok-Kyu Lee
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In this paper, we describe a FPGA implementation of MIMO detector for future wireless communication system with application to wireless LAN, targeted for upcoming 802.11n standard. The MIMO detector assumes 2 transmit and 3 receive antennas. In soft-output demapper, we apply channel state information which effectively weights reliability information to soft-decision output bits for enhanced link-level performance. The implementation complexity is significantly reduced by avoiding repeated pseudo-inverse calculation for interference cancellation of every received symbol vector. Furthermore, the overall processing time and fabrication area it takes can be significantly reduced by applying bit reduction technique

Published in:

2006 IEEE 63rd Vehicular Technology Conference  (Volume:5 )

Date of Conference:

7-10 May 2006