A macrocell approach for VLSI processor design

An effective layout design method for VLSI processors, called the `macrocell approach' is presented. The approach bridges the gap between full manual layout and polycell/standard cell layout with respect to the design productivity and the performance. After precise floorplanning, functional blocks are designed into macrocells using a flexible symbolic layout method, and a VLSI chip is laid out by an automatic layout program. A 16-bit digital signal processor (DSP) was designed using 2-μm CMOS technology. Both high packing density of 1150 transistors/mm² and high productivity of 6.5 transistors/day for symbolic layout were attained in the design. After fabrication, the chip operated with the first silicon, realizing high-speed operation in an application program for a 32-kb/s ADPCM CODEC (adaptive differential pulse-code modulated coder-decoder)