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Implementation of VLSI self-testing by regularization

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2 Author(s)
Younggap You ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; Hayes, J.P.

A novel circuit design methodology is developed for comprehensive offline self-testing of nearly regular VLSI circuits. It is based on four major design techniques: circuit partitioning, regularization to produce identical subcircuits (modules), parallel testing of modules, and fault detection by direct comparison of response streams from the modules. A generalization of I-testing called sequential I-testing (SI-testing) is described, which allows identical response streams to be produced at different times and be subsequently synchronized for comparison purposes. The concepts of k-regular and nearly k -regular circuits are introduced, which generalize regular circuits (iterative logic arrays) to array-like circuits that contain several cell-types and are moderately irregular. A heuristic circuit partitioning and regularization method for nearly-regular circuits is described

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:7 ,  Issue: 12 )