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SPIDER: capacitance modelling for VLSI interconnections

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2 Author(s)
Z. -Q. Ning ; Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands ; P. M. Dewilde

An efficient method is presented to model the parasitic capacitance of VLSI interconnections. It is valid for conductors in a stratified medium which is considered to be a good approximation for the Si-SiO/sub 2/ system of which ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a 'spider' of edges. The model has very low complexity as compared to previously presented models and achieves a high degree of precision within the range of validity of the stratified medium.<>

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:7 ,  Issue: 12 )