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Space efficient ESD methodology for reliable high volt applications

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3 Author(s)
Naughton, J.J. ; AMI Semicond., Pocatello, ID ; Tyler, M. ; Anser, M.

LDMOS-SCR structures have been shown to provide formidable ESD protection. This work characterizes CMOS process regions widely used in high voltage technologies to control triggering characteristics >40V. This is done using the breakdown voltage of a standard gate poly structure and structures without gate oxide further enhancing reliability during an ESD event

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Microelectronics and Electron Devices, 2006. WMED '06. 2006 IEEE Workshop on

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