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A New Built-In Self-Test Design for PLA's with Hligh Fault Coverage and Low Overhead

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3 Author(s)
Treuer, R. ; Department of Electrical Engineering, McGill University ; Agarwal, V.K. ; Fujiwara, H.

This correspondence presents a new built-in self-test design for PLA's, that has a lower area overhead and higher multiple fault coverage (of three types of faults: crosspoint, stuck, and bridging) than any existing design. This new design uses function independent test input patterns (which are generated on chip), compresses the output responses into a function independent string of parity bits (whose fault-free expected values are generated on-line with a simple circuit), and detects all siqgle faults and more than ( 1 −−2(m+2n) of all multiple faults where m and n represent the number of product terms and input variables, respectively.

Published in:

Computers, IEEE Transactions on  (Volume:C-36 ,  Issue: 3 )

Date of Publication:

March 1987

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