Cart (Loading....) | Create Account
Close category search window

A New Approach to the Design of Testable PLA's

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Reddy, S.M. ; Department of Electrical and Computer Engineering, University of Iowa ; Dong Sam Ha

Programmable logic arrays (PLA's) are extensively used to realize area efficient combinational logic circuits. As the size of the PLA's increases, a cost-effective way to test them is to realize testable PLA's. In this paper a new approach to the design of testable PLA's is presented. The proposed method leads to testable PLA's with minimal area penalty and small number of tests that can be obtained as a by-product of the synthesis procedure, or can be directly obtained from the personality of the PLA's, thus simplifying the test derivation step. Results of an experiment involving 56 PLA's, to compare the test set sizes of differenit testable PLA designs (including the design proposed here) as well as the size of tests derived to detect single faults by algorithmic procedures are also reported.

Published in:

Computers, IEEE Transactions on  (Volume:C-36 ,  Issue: 2 )

Date of Publication:

Feb. 1987

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.