By Topic

Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Lai, H.C. ; Fujitsu Microelectronics, Inc. ; Muroga, S.

Design of logic networks, in single-rail input logic, with a minimum number of NOR gates for parity functions of an arbitrary number of variables is described. This is partly based on minimum networks for parity functions of a small number of variables which are designed by the integer programming logic design method. Although it is generally difficult to design minimum networks for functions of an arbitrarily large number of variables, we have previously designed minimum networks for adders of an arbitrary number of variables. The minimum networks for parity functions of an arbitrary number of variables discussed in this paper is another case. Many unique properties of minimum NOR networks for parity functions are shown. Minimum networks with NAND gates for parity functions can be easily obtained from those with NOR gates because of duality relationship between NAND and NOR.

Published in:

Computers, IEEE Transactions on  (Volume:C-36 ,  Issue: 2 )