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An Alternative to Scan Design Methods for Sequential Machines

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2 Author(s)
Saluja, K.K. ; Department of Electrical and Computer Engineering, University of Wisconsin ; Dandapani, R.

The problem of testing sequential machines using a checking experiment is investigated. An algorithm is given to augment sequential machines by adding extra input(s) to make them testable. We also present a circuit modification method, similar to scan methods, such that the augmented machine can be tested by the checking experiment. A justification of our method for a VLSI environment is given by determining the overheads.

Published in:

Computers, IEEE Transactions on  (Volume:C-35 ,  Issue: 4 )

Date of Publication:

April 1986

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