Referenced Items are not available for this document.
A method for the deductive fault simulation of faults in inverter-free circuits is presented. It is shown that in an inverter-free circuit, fault lists on lines with complementary logic values are disjoint, and fault list calculations can be done by performing fewer set operations compared to conventional gate level deductive simulation. Applications of the method to programmable logic arrays (PLA's) and deductive fault simulation of PLA faults are discussed.
Published in:
Computers, IEEE Transactions on
(Volume:C-35
,
Issue:
1
)
Date of Publication: Jan. 1986
- Page(s):
- 70 - 73
- ISSN :
- 0018-9340
- Digital Object Identifier :
- 10.1109/TC.1986.1676661
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 21 August 2006
- Issue Date :
- Jan. 1986
- Sponsored by :
- IEEE Computer Society
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