By Topic

Square-Rooting Algorithms for High-Speed Digital Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
S. Majerski ; Instytut Maszyn Matematycznych

Two binary algorithms for the square rooting of a number or of a sum of two numbers are presented. They are based on the classical nonrestoring method. The main difference lies in the replacement of subtractions and additions by a parallel reduction f three summands, which may be positive and negative, to two summands to eliminate the carry propagation. Two of three summands form the successive partial remainder. Their most significant bit triples, sometimes together with a sign bit of the earlier partial remainder, are used to determine digits -1,0, +1 of a redundant square-root notation. These digits are transformed during the square-rooting process into the conventional notation square-root bits which are next used in further square-rooting steps to form the third reduced summands.

Published in:

IEEE Transactions on Computers  (Volume:C-34 ,  Issue: 8 )