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Fault Tolerance in Binary Tree Architectures

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3 Author(s)
Raghavendra, C.S. ; Department of Electrical Engineering-Systems, University of Southern California ; AVIvizienis, A. ; Ercegovac, M.D.

Binary tree network architectures are applicable in the design of hierarchical computing systems and in specialized high-performance computers. In this correspondence, the reliability and fault tolerance issues in binary tree architecture with spares are considered. Two different fault-tolerance mechanisms are described and studied, namely: 1) scheme with spares; and 2) scheme with performance degradation. Reliability analysis and estimation of the fault-tolerant binary tree structures are performed using the interactive ARIES 82 program. The discussion is restricted to the topological level, and certain extensions of the schemes are also discussed.

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Computers, IEEE Transactions on  (Volume:C-33 ,  Issue: 6 )