Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

An Efficient Implementation of Search Trees on [lg N + 1] Processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
2 Author(s)
Carey, M.J. ; Department of Computer Science, University of Wisconsin ; Thompson, C.D.

A scheme for maintaining a balanced search tree on γlg N + 1γparallel processors is described. The scheme is almost fully pipelined: γlg N + 1γ/2 search, insert, and delete operations may run concurrently. Each processor executes 0(1) instructions of a top-down 2-3-4 tree manipulation algorithm before passing the operation along to the next processor in the pipeline. Thus, the total delay per tree operation is O(lg N), and one tree operation completes every 0(1) time units.

Published in:

Computers, IEEE Transactions on  (Volume:C-33 ,  Issue: 11 )