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A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays

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2 Author(s)
Ramanatha, K.S. ; Department of Electrical Engineering, Government B.. . College of Engineering ; Biswas, N.N.

In this paper, the validity of single fault assumption in deriving diagnostic test sets is examined with respect to crosspoint faults in programmable logic arrays (PLA's). The control input procedure developed here can be used to convert PLA's having undetectable crosspoint faults to crosspoint-irredundant PLA's for testing purposes. All crosspoints will be testable in crosspoint-irredundant PLA's. The control inputs are used as extra variables during testing. They are maintained at logic 1 during normal operation. A useful heuristic for obtaining a near-minimal number of control inputs is suggested. Expressions for calculating bounds on the number of control inputs have also been obtained.

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Computers, IEEE Transactions on  (Volume:C-32 ,  Issue: 6 )