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Design and Performance of Generalized Interconnection Networks

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2 Author(s)
L. N. Bhuyan ; Department of Electrical and Computer Engineering, University of Southwestern Louisiana ; D. P. Agrawal

This paper introduces a general class of self-routing interconnection networks for tightly coupled multiprocessor systems. The proposed network, named a "generalized shuffle network (GSN)," is based on a new interconnection pattern called a generalized shuffle and is capable of connecting any number of processors M to any number of memory modules N. The technique results in a variety of interconnection networks depending on how M nd N are factored. The network covers a broad spectrum of interconnections, starting from shared bus to crossbar switches and also includes various multistage interconnection networks (MIN's).

Published in:

IEEE Transactions on Computers  (Volume:C-32 ,  Issue: 12 )