Referenced Items are not available for this document.
This paper describes by a series of examples a strategy for designing testable fault-tolerant arrays of processors. The strategy achieves fault tolerance by introducing redundancy in an array's communication links rather than in its processing elements (PE's). The major characteristics of the designs produced are as follows.
Published in:
Computers, IEEE Transactions on
(Volume:C-32
,
Issue:
10
)
Date of Publication: Oct. 1983
- Page(s):
- 902 - 910
- ISSN :
- 0018-9340
- Digital Object Identifier :
- 10.1109/TC.1983.1676134
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 21 August 2006
- Issue Date :
- Oct. 1983
- Sponsored by :
- IEEE Computer Society
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