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The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors

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1 Author(s)
A. L. Rosenberg ; Department of Computer Science, Duke University

This paper describes by a series of examples a strategy for designing testable fault-tolerant arrays of processors. The strategy achieves fault tolerance by introducing redundancy in an array's communication links rather than in its processing elements (PE's). The major characteristics of the designs produced are as follows.

Published in:

IEEE Transactions on Computers  (Volume:C-32 ,  Issue: 10 )