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A Regular Layout for Parallel Adders

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2 Author(s)
Brent, Richard P. ; Department of Computer Science, Australian National University ; Kung, H.T.

With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.

Published in:

Computers, IEEE Transactions on  (Volume:C-31 ,  Issue: 3 )