Cart (Loading....) | Create Account
Close category search window
 

Comparative Performance Analysis of Single Bus Multiprocessor Architectures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Ajmone Marsan, M. ; Istituto di Elettronica e Telecomunicazioni, Politecnico di Torino ; Balbo, G. ; Conte, G.

Markovian models are developed for the performance analysis and comparison of several single bus multiprocessor architectures. Processors are assumed to cooperate in a message passing fashion, and messages are exchanged through common memory areas. Four architectures are considered in this paper which differ in the location of the common memory modules. Contention for shared resources is modeled and the corresponding efficiency loss is studied. Numerical results are obtained for the processing power of each architecture, introducing simplifying assumptions that allow a compact Markovian system description.

Published in:

Computers, IEEE Transactions on  (Volume:C-31 ,  Issue: 12 )

Date of Publication:

Dec. 1982

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.