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Memory Interference in Synchronous Multiprocessor Systems

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3 Author(s)
Yen, D.W.L. ; IBM San Jose Research Laboratory ; Patel, J.H. ; Davidson, E.S.

Synchronous N-processor systems with M shared memories are considered. Memory interference is modeled for processor request rates between 0 and 1 per memory cycle. Two probability-based models and one queueing-based model are summarized from prior literature. A new steady-state flow model is introduced. This steady-state model is most accurate overall. The queueing model is somewhat more accurate when request rate is near 1, and M and N are large. Accuracy is established with respect to probabilistic simulation. Additional related models are described.

Published in:

Computers, IEEE Transactions on  (Volume:C-31 ,  Issue: 11 )

Date of Publication:

Nov. 1982

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