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A multiple microprocessor system is described which was developed for real-time detection and classification of railroad track flaws. Multiple processors were necessary to achieve the desired test vehicle velocity while maintaining the desired density (rate) of testing. The system is organized logically as a tree-structured pipeline of processing stages where the effective data rate from data input toward classification decision output is successively reduced as processing function potential is increased. A corresponding partitioning of the pattern recognition process was organized as a set of hierarchies, where successive patterns are modeled as regular probabilistic grammars and their recognizers implemented as finite state procedures. Interprocessor communications was achieved using shared (2-port) memories. A system prototype was designed and implemented, using real-time data from earlier work to ensure a performance level equivalent to a vehicle velocity of 40 km/h. The resulting system, while applied to a railroad track problem, is applicable to other real-time environments, with suitable parameterization.