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Implementation and Performance Evaluation of Computer Families

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2 Author(s)
Snow, E.A. ; Intel Corporation ; Siewiorek, D.P.

This correspondence proposes a model using microcycle and memory read pause times to account for variation in performance between members of a computer family. Wben applied to the DEC PDP-11 and IBM S/360-S/370 families, the model explains over 90 percent of the variation. This model is useful for initial family planning, as well as design of individual family members.

Published in:

Computers, IEEE Transactions on  (Volume:C-30 ,  Issue: 6 )