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A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks

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2 Author(s)
Se June Hong ; IBM T. J. Watson Research Center ; Ostapko, D.L.

A simple procedure to produce a minimum length test set for a parity network is presented. If M is the largest fan in of any EX-OR gate element in the tree, 2M test patterns are chosen by considering only 2M test sequences, of length 2M, assigned to each signal line.

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Computers, IEEE Transactions on  (Volume:C-30 ,  Issue: 5 )