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Optimal Layout of CMOS Functional Arrays

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2 Author(s)
Uehara, T. ; Computer Science Laboratory, Fujitsu Laboratories ; Vancleemput, W.M.

Designers of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance. This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented. This method is useful for the design of cells used in conventional design automation systems.

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Computers, IEEE Transactions on  (Volume:C-30 ,  Issue: 5 )