Rewritable Programmable Logic Array of Current Mode Logic

This paper describes new ways to construct a rewritable programmable logic array (R-PLA) of current mode logic (CML) and to control READ/WRITE operations of the R-PLA. The R-PLA is constructed by splitting a conventional Random Access Memory (RAM) of CML into two parts. Therefore, each cell structure of the new R-PLA is identified with that of the conventional RAM, differing from a complicated cell structure proposed in the past. Because of the identification the comparison for the number of cells between the new R-PLA and the RAM becomes possible according to the historical discussions of the PLA and the memory. It will be demonstrated logically and electrically that SEARCH and READ parts of the new R-PLA can perform logic-in-memory without using special AND gates in each cell in the READ mode and can enter a WRITE data from a word direction in the WRITE mode.