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A Design of Programmable Logic Arrays with Universal Tests

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2 Author(s)
Fujiwara, H. ; Department of Electronic Engineering, Osaka University ; Kinoshita, K.

In this paper the problem of fault detection in easily testable programmable logic arrays (PLA's) is discussed. The easily testable PLA's will be designed by adding extra logic. These augmented PLA's have the following features: 1) for a PLA with n inputs and m columns (product terms), there exists a "universal" test set such that the test patterns and responses do not depend on the function of the PLA, but depend only on the size of the PLA (the values n and m); 2) the number of tests is of order n + m. For the augmented PLA's, universal test sets to detect faults in PLA's are presented. The types of faults considered here are single and multiple stuck faults and crosspoint faults in PLA's. Fault location and repair of PLA's are also considered.

Published in:

Computers, IEEE Transactions on  (Volume:C-30 ,  Issue: 11 )