By Topic

Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Galiay, J. ; Société pour l''Etude et la Fabrication de Circuits Intégrés Spéciaux (EFCIS) ; Crouzet, Y. ; Vergniault, M.

At the end of an IC production line, integrated circuits are generally submitted to three kinds of tests: 1) parametric tests to check electrical characteristics (voltage, current, power consumption), 2) dynamic tests to check response times under nominal operating conditions, and 3) functional tests to check its logical behavior.

Published in:

Computers, IEEE Transactions on  (Volume:C-29 ,  Issue: 6 )