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The performance of pipelined processors is heavily influenced by the effects of control-transfer, or branching, instructions, and various strategies have been used to reduce the delays incurred by these instructions. The position of the "control point" in the pipeline is an important factor that must also be taken into account, however, and this paper presents an analysis of its effects. Results are given of measurements made with a hardware performance monitor during the running of benchmark programs on the highly pipelined MU5 processor. These results support the argument for placing the control point as late in the pipeline as possible, and for using a prediction mechanism to supply correct sequences of instructions to the pipeline.