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Ternary Rate-Multipliers

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3 Author(s)
Mouftah, H.T. ; Department of Electrical Engineering, Queen''s University ; Smith, K.C. ; Vranesic, Z.G.

This correspondence describes an application of COS/MOS integrated circuits in the design of ternary rate-multipliers. The logical implementation of two types of ternary rate-multiplier is described. The first type produces an unevenly spaced output pulse train, while in the second one the output pulses are uniformly spaced. Advantages and disadvantages of the two types are presented.

Published in:

Computers, IEEE Transactions on  (Volume:C-29 ,  Issue: 10 )