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Toggle-Registers Generating in Parallel k kth Decimations of m-Sequences xP+ xk+ 1 Design Tables

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2 Author(s)
Arvillias, A.C. ; Nuclear Research Center Democritos, Digital Systems Laboratory, Computer Center ; Maritsas, D.G.

For the class of primitive trinomials xP+ xk+ 1 with (k, 2P-1) = 1, shift register constructions are presented which are designed to produce in parallel consecutive patterns, of k-consecutive bits each, of the corresponding m-sequence. The resultant class of register structures preserves the function of equivalent feedback shift registers (FSR's) with composite feedback logic while allowing a saving in the physical implementation which amounts to the complete elimination of modulo-2 adders. This accounts for the high-speed performance of the toggle-registers presented, and makes them suitable for a broad range of applications.

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Computers, IEEE Transactions on  (Volume:C-28 ,  Issue: 2 )