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A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems

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1 Author(s)
Reddy, S.M. ; Division of Information Engineering, University of Iowa

To improve the reliability of computer memories error-correcting and/or error-detecting codes have been successfully used. To provide for error control in systems organized to have b bits per card a new class of codes for simultaneous error correction and error detection is given.

Published in:

Computers, IEEE Transactions on  (Volume:C-27 ,  Issue: 5 )