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Minimizing Latency in CCD Memories

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2 Author(s)
Fuller, S.H. ; Department of Computer Science, Carnegie-Mellon University ; McGehearty, P.F.

Serial memories built from charge-coupled devices (CCD's) offer an opportunity for minimizing latency times not available with the more conventional drum and disk (serial) memory units. Let r be the ratio of the maximum to the minimum clocking rates for the CCD memory. We show that in many practical situations the average latency can be reduced from 1/2 to 1/(1 + √r) of a revolution time if the optimal clocking strategy is used when the CCD is idle.

Published in:

Computers, IEEE Transactions on  (Volume:C-27 ,  Issue: 3 )

Date of Publication:

March 1978

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