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This paper is concerned with optimal synthesis of switching logic by a limited depth tree-like network, the NAND cascade. This cascade consists of a number of complete three-level, fan-in restricted NAND trees feeding a NAND collector. The goal of the proposed synthesis is to minimize the number of NAND trees of the cascade, which in turn will minimize its overall depth, i.e., the delay time of the cascade.
Date of Publication: Dec. 1978